(1) Field of the Invention
The invention relates to a self-aligned contact process and more particularly to a contact etching process of high etching selectivity by using silicon spacers.
(2) Description of the Prior Art
As semiconductor devices continually progress towards denser packing of active devices, the alignment between the mask and the device becomes an extremely important issue. Owing to the limitation of the photo lithographic process, misalignment in the masking process is unavoidable. Although the misalignment can be compensated by enlarging misalignment tolerance in circuit designing, however the increase of device dimension makes it less favorable in the trend of high packing density. In order to solve the problem of misalignment in the masking process and to further minimize the device size, a contact etching process known as self-alignment contact (SAC) process is surfaced over the past few years.
A typical self-aligned contact, as shown in FIG. 1, would be formed by a process, comprising: receiving a semiconductor substrate 10 having gate structures formed thereon, the gate structure comprising a layer of gate oxide 11 and at least a layer of conducting material 12; depositing an overall conformal layer of silicon nitride, then anisotropically etching back the silicon nitride layer to form side wall spacers 13 on both sides of the gate structure; thereafter, providing and planarizing an overall inter layer dielectric 14, the inter layer dielectric 14 is then anisotropically etched to form the self-aligned contact with the aid of a patterned mask. During the contact etching process the gate structure is protected by the side wall spacers 13, thus the etching process is confined to the region between the side wall spacers 13 to form the self-aligned contact window.
The side wall spacers protect the gate structure from undercutting in the contact etching process when misalignment occurred in the masking process. However, due to low etching selectivity between the side wall spacers and the inter layer dielectric, a great part of the side wall spacers is consumed in the contact etching process. The damage of side wall spacers usually leads to a short circuit in the metallization process and much effort has been directed to modify the fabrication process, especially on the etching process, to make the self-aligned contact process more reliable.